This invention relates to analog-to-digital (A/D) converters, and more particularly to circuitry for high speed conversion of analog signals to digital signals.
Analog-to-digital converters are widely employed for converting analog voltages into corresponding digital signals for processing by digital computers, and have been constructed according to a number of alternative approaches. One approach involves integrating the analog input signal to generate a ramp signal of a predetermined slope and for a time corresponding to the analog input. This technique is disclosed, for example, in U.S. Pat. No. 4,647,905 (Hantke et al) granted Mar. 3, 1987, showing a circuit with three integrators, each including an operational amplifier and a capacitor wired to the amplifier. Similarly, U.S. Pat. No. 4,558,301 (Trofimenkoff) granted Dec. 10, 1985 discloses a voltage-to-frequency and analog-to-digital conversion circuit utilizing a microprocessor to control the charge and discharge of a capacitor.
Another approach, known as successive approximation, is shown in U.S. Pat. No. 4,323,887 (Buurma) granted Apr. 6, 1982, employing CMOS construction in converting a digital word to analog voltages which are compared with the analog input. The most significant bit of the digital word is determined in accordance with whether the analog input is greater or less than half of the reference voltage. Then, the next most significant bit is evaluated, with the process continuing until evaluation of the least significant bit.
For higher speed applications, a parallel conversion technique may be employed as described in U.S. Pat. No. 4,644,322 (Fujita) granted Feb. 17, 1987. The A/D converter in Fujita includes a voltage divider having 2.sup.n junctions connected in series between a reference voltage terminal and a ground terminal, along with 2.sup.n comparators for receiving outputs of the respective divider junction. This technique, also known as flash conversion, requires at least 2.sup.n -1 comparators to produce a digital word of n bits representative of the analog signal.
Another high speed conversion technique combines a flash approach with successive approximation. A hybrid converter digitizes a group of the most significant bits, for example the first four, and converts these bits into an analog signal, which is then subtracted from the analog input. The difference is amplified and converted to a digital signal. This converter uses 2.sup.n -1 comparators for the n most significant bits, 2.sup.m -1 comparators for the m least significant bits, and one further comparator.
While the above devices all have utility in certain applications, the above-discussed parallel conversion and hybrid devices have a comparator requirement that increases exponentially with the number of desired bits. Such devices therefore become prohibitively complex. On the other hand, the integration and successive approximation approaches are considered too slow for many uses. There remains a need for a simple, low cost and reliable A/D converter capable of operating at high speeds and with high precision.
Therefore, it is an object of the present invention to provide an analog-to-digital converter having a complexity directly proportional to the desired precision or number of bits in the digital word output.
Another object of the invention is to provide an A/D converter requiring no preliminary processing of the input analog signal and operable without a clock.
Another object is to provide an A/D converter comprised of multiple, substantially identical stages.
Yet another object is to provide a reliable A/D converter manufactured as a low cost integrated circuit requiring a minimal amount of space on an IC chip.